Texas Instruments OMAP5912 Reference Manual page 130

Multimedia processor device overview and architecture

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Wait States During a Read to Write Transition (BTWST(CSX)= 3 BTWST

(CSY) = 2, BTMODE=0)

FL_DIR_O(DATAEN)

(FROM FLASH)

OMAP3.2 Subsystem

The BTMODE field in the advance CS configuration register (see

Table 28) extends the previous mode. When BTMODE=1, BTWST bit field

controls CS negation time between any type of successive accesses to

the same CS.

In case of successive write accesses due to EMIFS access size

adaptation or in case of write burst read access, there is no CS negation

time between successive write accesses unless BTMODE is set. When

BTMODE is set, the CS negation time between the successive write

accesses is at least one TC_CK cycle and it can be extended by the

BTWST field in the CS configuration (see Table 19) register (BTMODE set

CS pulse width high= (BTWST +1) TC_CK

Table 2 shows the idle cycles inserted for various transitions with EMIFS

when BTMODE=1.

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