Texas Instruments OMAP5912 Reference Manual page 618

OMAP5912 Power Modes
100 Power Management
4) DSP wake-up from sleep state
In this case, the wake-up is handled entirely by the MPU software. There is
no wake-up path through DSP interruptions.
a) The MPU sets the GPIOs that control the external analog switch to
power on the DSP domain. (It can also be done through an SPI/I
interface.)
b) The MPU waits during the ramp-up time of the DSP domain VDD.
c) The MPU programs the ULPD POWER_CTRL_REG[12] to release
the ISOLATION_CONTROL bit to deactivate the DSP domain
isolation wrapper.
d) The MPU enables the DSP clock by asserting the EN_DSPCK bit in
the ARM_CKCTL register of CLKRST.
e) The MPU releases the DSP reset state by deasserting the DSP_EN
and DSP_RST bits into the ARM_RSTCT1 register of the CLKRST
module.
f) The DSP boots.
5) MPU wake-up from inactive state
a) Any unmasked interrupt in the MPU interrupt handler is
asynchronously forwarded to ULPD: theWAKEUP_REQ signal is
asserted.
b) If DSP is also in inactive state, any unmasked interrupt in the DSP
interrupt handler is asynchronously forwarded to the ULPD: the
WAKEUP_REQ signal is asserted.
c) ULPD detects wake-up request: WAKEUP_REQ or clock request at
ULPD
d) ULPD FSM automatically moves into its awake mode and enables the
OMAP3.2 input clock.
e) The DPLL clock restarts automatically.
f) The MPU and TC clocks restart automatically.
6) MPU active to inactive state transition
a) The MPU places the external SDRAM in self-refresh mode (program
EMIFF register).
b) The MPU programs the ARM_IDLECT1, ARM_IDLECT2, and
ARM_IDLECT3 registers to ensure that all OMAP MPU and TC
subdomain clocks are shut down.
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