Texas Instruments OMAP5912 Reference Manual page 481

Configuration
Table 33. USB Transceiver Control Register (USB_TRANSCEIVER_CTRL)
(Continued)
Bit Name
6:4 CONF_USB_PORT0_R
3 CONF_USB0_ISOLATE_R
2 CONF_USB_PWRDN_DM
_R
1 CONF_USB_PWRDN_DP_
R
0 RESERVED
Table 34. LDO Powerdown Control Register (LDO_PWRDN_CNTRL)
Bit Name
31:1 UNUSED
0 CONF_LDO_PWRDN_
CNTRL_R
64 Initialization
Base Address = 0xFFFE 1000, Offset Address = 0x64
Function
These bits control the multiplexing on the I/O,
which defaults to USB.DP and USB.DM at
reset.
These 3 bits configure USB port 0 for
alternate operation.
COMP_MODE_CTRL_0 must be
programmed to 0xEAEF for this register to
control functional multiplexing.
000: USB.DP/USB.DM
100: I2C.SDA/I2C.SCl
101: UART1.RX/UART1.TX
111: USB2.PUEN/HI-Z
Other values are not allowed. Programming
this field on some other value produces
unpredictable results.
Isolates the USB port 0 controller from the
integrated USB transceiver.
0: Normal mode
1: Isolation mode
Enable/disable of pulldown on USB DM pin.
0: Enable of pulldown on DM
1: Disable of pulldown on DM
Enable/disable of pulldown on USB DP pin.
0: Enable of pulldown on DP
1: Disable of pulldown on DP
Reserved for future expansion.
Base Address = 0xFFFE 1000, Offset Address = 0x68
Function
These bits are not implemented.
If the user sets LDO_PWRDN to 1, the LDO
can be powered-down and bypassed.
R/W Reset
R/W 0x0
R/W 0x0
R/W 0x1
R/W 0x1
R/W 0x0
R/W Reset
R 0x00000000
R/W 0x0
SPRU752B