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SPI Master/Slave
1.4
Protocol Description
28
Serial Interfaces
FDO: This control bit enables forcing TSPDO to read the value of the WTV
-
bit, allowing control of TSPDO.
WTV: This bit enables the forcing the TSPDO value (test purposes).
-
RTV: This bit is directly connected to TSPDI. It assumes that the input
-
signal is static.
WCV: This bit enables forcing the CLK output (in master mode only) to
-
provide control of the CLK output.
RCV: This bit is directly connected to CLK input. It enables testing
-
connectivity of CLK_S in feedback mode only.
RTSPEN: These bits are directly connected to TSPEN outputs when the
-
test mode is enabled.
The serial port interface must be configured via the setup registers.
A read process is always simultaneous with a write process, because the
internal shift register is based on a loop (FIFO principle). However, the
concurrent write process can be a dummy write if there is no data to transmit.
Depending on the mode selection (master or slave mode), the shift register
clock can be derived internally from the CLK_M, or it can come directly from
the CLK_S input.
The external transfer of a packet starts as soon as one of the transmit clocks
is generated.
The received/transmitted data packet is shifted in/shifted out on the rising or
falling edge of the shift register clock (SRCLK).
The loading of the packet is then validated on the deactivation of the enable
signal (rising or falling edge).
SPI_ISR is updated at the end of a transaction in MCU-DSP and DMA modes
(master or slave), and an interrupt request can be generated depending on
SPI_IER bits.
Sections 1.4.1 to 1.4.3 present the steps describing the MCU-DSP and DMA
protocols. These steps must be followed in order to have a correct behavior.
In MCU-DSP protocol, the interrupt request must not be masked. Thus, the
SPI can issue an interrupt to inform the host that the transaction is
finished.
SPRU760B
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