Texas Instruments OMAP5912 Reference Manual page 788

DSP DMA
Table 112. Channel Control Registers (DMA_CCR0...DMA_CCR5) (Continued)
Bit Name
5 FS
4:0 SYNC
164 Direct Memory Access (DMA) Support
Function
Frame synchronization
This bit determines whether the synchronization
event initiates the transfer of an element or an
entire frame of data.
0: When the selected synchronization event
occurs, one element is transferred in the channel.
Each element waits for the synchronization event.
1: When the selected synchronization event
occurs, an entire frame is transferred in the
channel. Each frame waits for the synchronization
event.
Synchronization control
This field is used to specify which event in the DSP
(for example, timer1 countdown) initiates a DMA
transfer in this channel. There are 20 possible
choices, and multiple channels can share the
same synchronization event. That is, one event
can initiate the transfer in multiple DMA channels.
0000: Transfer not synchronized
i: Transfer synchronized on DMA_REQUEST[i].
The behavior of DMA synchronized transfers is
described in Section 4.13, Synchronizing Channel
Activity.
Table 113 shows the DSP DMA mapping.
Type Reset
0 RW
00000 RW
SPRU755B