Texas Instruments OMAP5912 Reference Manual page 138

Multimedia processor device overview and architecture
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3.3.5
EMIFF Configuration Power−Down Considerations
80
OMAP3.2 Subsystem
-
Entering self-refresh (SLRF bit). The self-refresh mode is automatically
exited when the EMIFF receives an access request from OMAP initiators.
You can set the refresh counter value corresponding to system frequency. The
following formula can be used for refresh counter value (the counter value is
the number of TC_CK between refreshes).
Counter value = (64 ms (refresh rate) / Number of row / t
50 cycles margin due to a possible transfer currently starting when the refresh
request occurs.
Where t
= 1/system frequency [ns] (system freq = TC_CK freq)
f
Example: 100-MHz system clock, 4096 rows and 8-burst refresh. t
Counter value = ((64.10
Counter value = 1512 cycles (0x5E8)
If burst autorefresh is selected (4 or 8 consecutive autorefresh commands),
this refresh period value is automatically scaled by the hardware accordingly.
Self−refresh commands will not be issued and the SDRAM clock enable (CKE)
will not deactivate under the following conditions:
J
EMIFF_CONFIG.pwd = 1
J
EMIFF_CONFIG.clk = 0
J
EMIFF_CONFIG2.sd_auto_clk = 1
In addition, when in DPD (deep power down) mode, the SLRF bit must not be
set because the CKE cannot operate after DPD exit.
6
ns/4096)/10) − 50
) − 50 cycles
f
= 10 ns.
f
SPRU749A

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