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Table 43. NAND Controller System Test Register (NND_SYSTEST)
Bit
Name
31-16 Reserved
15
TEST-UNLO
CK
14-3
Reserved
2
MAP
1
ACCESS
0
ALLOW_INT If 1, can initiate an interrupt
SPRU756A
Reserved
To unlock test features
Reserved
When 1, the internal FIFO is mapped as registers.
If 1, unlock registers for read/write access
This register tests some features of the NFC. There is a special scheme to
access it.
-
Bits 31-16: Reserved
-
Bit 15: This bit must be set initially, and then for each other access be kept
to 1 by the local host, to allow the local host to set/clear other register-bit
positions in this test register on subsequent accesses. Hence, to perform
a successful set in another bit position, two successive accesses are
st
required: the 1
subsequent accesses to set another bit position to 0/1 while keeping
TEST_UNLOCK to 1. If TEST_UNLOCK is 0, the full sequence needs to
take place again.
-
Bits 14-3: Reserved
-
Bit 2: This bit, when 1, maps the FIFO to the addressable space of
registers. The FIFO is mapped from address 0x64 to 0x70. Those
registers are accessible only in test mode; in normal mode, accessing
these registers returns an error.
-
Bit 1: When set, all registers become accessible in read and in write
(except the NND_REV register). All pins to NFMC are inactive. It is
possible to write a value up to 32 bits in the buffer, thus generating an
interrupt, and reading back the NAND controller access register
(NND_ACCESS).
-
Bit 0: Normally, the pending interrupt bits of the NND_STATUS register are
set to 1 only when an interrupt is generated; the software cannot initiate
an interrupt. By writing a 1 to the ALLOW_INT bit, the software can write
a 1 in the interrupt bit of the NND_STAUS, thereby initiating an interrupt.
Description
access to set the TEST_UNLOCK bit to 1, and the 2
Memory Interfaces for the EMIFS
Type
RW
RW
RW
RW
RW
RW
Memory Interfaces
Reset
0
0
0
0
0
0
nd
and
69
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