Texas Instruments OMAP5912 Reference Manual page 722

System DMA
Table 55. DMA Channel Interrupt Control Register(DMA_CICR)
Base Address = 0xFFFE D800, Offset Address = 0x04 + n*0x40
Bit Name
15:6 RESERVED
5 BLOCK_IE
4 LAST_IE
3 FRAME_IE
2 HALF_IE
1 DROP_IE
0 TOUT_IE
98 Direct Memory Access (DMA) Support
DST_AMODE: Destination addressing mode
-
This field is used to choose the addressing mode on the destination port of
a channel.
dst_amode = 00: Constant address
dst_amode = 01: Post-incremented address
dst_amode = 10: Single index (element index)
dst_amode = 11: Double index (element index and frame index)
Function
Reserved
End block interrupt enable (end of block)
Last frame interrupt enable (start of last frame)
Frame interrupt enable (end of frame)
Half-frame interrupt enable (half of frame)
Synchronization event drop interrupt enable
(request collision)
Time-out interrupt enable (time-out error)
The interrupt enable bits are used to choose the events that cause the DMA
channel send an interrupt to the processor. There are two classes of events:
Error event: Errors during the transfer; for example time-out and event
-
drop.
Status event : DMA transfer status, during DMA channel transfers; for
-
example new frame starts, end of data block to transfer is reached.
Each time an event occurs, if the corresponding interrupt enable bit is set, the
channel sends an interrupt to the processor. At the same time, the
corresponding status bit is set in DMA_CSR (DMA channel status register). A
status bit is not set, if the corresponding interrupt enable bit in the DMA_CICR
equals 0.
TOUT_IE: Time-out interrupt enable (time-out error)
-
tout_ie = 1: The DMA sends an interrupt to the processor if a time-out error
occurs either in the source or in the destination port of the channel.
tout_ie = 0: The DMA does not send an interrupt to the processor if a time-
out error occurs.
R/W Reset
R/W N/A
R/W 0
R/W 0
R/W 0
R/W 0
R/W 1
R/W 1
SPRU755B