Texas Instruments OMAP5912 Reference Manual page 193

SPRU749A
(DSP_IDLECT1 and DSP_IDLECT2), different parts of the DSP subsystem go
to idle mode when the IDLE instruction is executed.
The following procedure describes how the DSP enters idle mode:
1) Disable the watchdog timer.
When the timer/watchdog timer is configured as a watchdog, its clock
(CK_REF/14) is never shut down.
2) Disable the following DSP peripheral clocks by setting the corresponding
bits in DSP_IDLECT2 register to 0s.
J
DSP external peripheral clock
J
External reference peripheral clock
This disables the clocks immediately, regardless of whether the DSP clock
is enabled or not. Or set the DSP_IDLECT1 corresponding bits to 1s,
which disables the DSP peripheral clocks only when the DSP clock is
disabled.
3) Switch the DSP TIPB and MPUI to shared access mode (SAM).
4) Program the DSP idle control register to put all the DSP subsystem
domains in idle mode.
5) Switch the DSP TIPB and MPUI to host-only mode.
6) Execute the IDLE instruction.
7) When IDLE_DSP = 1 in ARM_SYSST register, the DSP_CK stops.
8) A signal is sent to the OMAP DSP interrupt handler to disable the interrupts
to the DSP while the DSP clock is being disabled.
9) The DSP interrupt handler clock also stops after the synchronization
cycles end.
10) The DSP clock subdomain goes to idle mode when both the DSP and the
MPU clocks are disabled and the corresponding DSP_IDLECT1 bits are
set to 1.
Even when the DSP or MPU is not in idle mode, you have the option of
individually disabling the DSP domain clocks by setting the corresponding
DSP_IDLECT2 enable bits to 0s.
Clock Generation and Reset Management
OMAP3.2 Subsystem 135