Texas Instruments OMAP5912 Reference Manual page 205

Table 65. MPU Idle Enable Control Register 2 (ARM_IDLECT2)
Bit Name
31:12 RESERVED
11 EN_CKOUT_ARM
10:9 RESERVED
8 DMACK_REQ
7 EN_TIMCK
6 EN_APICK
5:4 RESERVED
3 EN_LCDCK
For reserved bits, reading gives undefined values. Writing to has no effect.
Note:
SPRU749A
Base Address = 0xFFFE CE00, Offset = 0x08
Function
See note.
This read-write bit enables the free running clock
from DPLL1 output
0: The clock generated from DPLL1 output is
stopped. This bit must be set to logic 1 to resume
clock activity
1: The clock generated from DPLL1 output is active
See note.
Disables the permanently-supplied-clock to the
system DMA controller to function on a clock request
basis.
0: The DMA clock is shutdown when the idle mode is
entered if IDLIF_ARM bit of ARM_IDLECTL1 is set.
1: The DMA clock is stopped by default and is
reactivated upon DMA request only.
Enables the MPU internal timer clock connected to
the MPU TIPB.
0: The MPU timer clock is stopped.
1: The MPU timer clock is active and can be stopped
depending of the IDLTIM_ARM bit of
ARM_IDLECTL1.
Enables the clock of the MPUI.
0: The MPUI clock is stopped. This bit must be set to
logic 1 to enable clock activity
1: The MPUI clock is active. The clock ON/OFF is
now controlled as per IDLAPI_ARM bit.
Reading these bits gives undefined values. Writing to
them has no effect.
Enables the clock of the LCD controller connected to
MPU TIPB.
0: The LCD clock is stopped.
1: The LCD clock is active.
Clock Generation and Reset Management
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
OMAP3.2 Subsystem
Reset
0000
0
00
1
0
0
00
0
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