Texas Instruments OMAP5912 Reference Manual page 141

3.3.8 DLL Control for DDR SDRAM Support
Figure 38. EMIFF DDR Data Reads (with respect to DLL)
Strobe (from
memory)
Data
T2
Internal
shifted strobe
Notes: 1) T1: Fine tune delay control for shift of internal strobe (a manual adjustment). 64 steps of adjustment with a step
value of 26.3ps (6 bit signed value in EMIFF_DLL_WRD_CTRL.WO). Note that 26.3 ps is a value valid in a nominal
process at room temp and is subject to variation across process and temperature.
2) T2: The EMIFF_DLL_WRD_CTRL .DLLP control bit selects whether the internal strobe is 72 or 90 degrees (20%
or 25% delay) from the external strobe
SPRU749A
The EMIF fast includes digitally controlled delay technology, for interfacing
high-speed double-data-rate memory components to meet the strict timing
requirements.
The DLL (delay locked loop) is a calibration module used to track voltage and
temperature variations dynamically, as well as to compensate the silicon
process dispersion (process voltage temperature (PVT) tracking). Two
separate DLL elements are used in the EMIFF—one to control the read timing
and one to control the write timing.
The DLLs controls several DCDL companion modules (digitally controlled
delay line). by providing an 8-bit value, continuously updated so that it encodes
a specific delay value (nominal 72 or 90 degrees) with respect to the memory
interface clock frequency, in all PVT conditions. The amount of delay added
by a DCDL element, controlled by this value under the same PVT conditions,
matches the DLL 72 or 90-degree nominal delay.
EMIFF uses two DLLs: one for read operations, the other for write operations.
The read DLL controls two DCDLs. Each DCDL shifts the upper byte
(respectively. lower byte) strobe coming from the DDR to ensure the data from
the DDR can be properly sampled (see Figure 38).
T1
The write DLL controls one DCDL. This DCDL is used to shift the data lines
from OMAP5912 to the DDR (see Figure 39).
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OMAP3.2 Subsystem 83