Texas Instruments OMAP5912 Reference Manual page 849

Figure 14. Single Page Read in Prefetch Mode
Software programs the address.
Software programs the read command.
Software programs the NND_CTRLFIFO
(FIFO_SIZE and BLOCK_COUNT field).
Software enables events if needed.
Software enables prefetch mode.
Note: ECC not represented.
2.1.14 Postwrite
SPRU756A
When prefetch goes from 1 to 0:
-
Prefetch is aborted.
Before accessing a new page, software must successively write 0 and then 1
in the prefetch bit. At reset, the prefetch bit is set to 0.
N.F.C fetches the data from the N.F.M.C and
fills the FIFO.
When FIFO is full, interrupt is asserted low.
Counter is decremented.
(n) (n)
(n)
Software reads the data from the FIFO.
Interrupt is cleared by software.
When FIFO empty, trigger a new prefetch.
After the host programs the address of the page to program, the command
program is sent, and the host enables the postwrite bit. The internal counter
is loaded with the BLOCK_COUNT value of the NND_FIFOCTRL register (see
Figure 15).
The software can write a FIFO_SIZE byte(s) in the FIFO of the NFC by
accessing NND_FIFO. When the FIFO is full, the NFC sends the data to the
NFMC, asserts the interrupt (if event FIFO_FULL is unmasked), and the
counter is decremented. When all of the data is sent, the FIFO is empty and
Memory Interfaces for the EMIFS
Last prefetch as counter = 0.
(n)
(n) (n)
Memory Interfaces
Ready/busy_
Flintn (interrupt)
43