Texas Instruments OMAP5912 Reference Manual page 194

Clock Generation and Reset Management
4.3.3 Traffic Controller, System DMA Controller, and MPU TIPB Bridges Idle
Control
Traffic Controller Idle Control
136 OMAP3.2 Subsystem
A wake-up sequence is initiated in DSP domain only upon one of the following
events:
J
A system reset
or
J
A DSP reset
or
J
An unmasked DSP interrupt request. The interrupt request restarts
the DSP clock if the WKUP_MODE bit of ARM_IDLECT1 is set to 1 or
if the chip is not in idle. In case of chip idle and WKUP_MODE set to 0,
the external wake-up control feature is enabled and a CHIP_nWKUP
low in conjunction with the interrupt required to wake up the DSP
clock.
On wake up, all the DSP subdomains put in idle mode using DSP_IDLECT1
are restarted following the sequence described below if corresponding enable
bits of ARM_IDLECT2 are set.
J
Service and clear the interrupt event.
J
Switch the DSP TIPB and MPUI to SAM mode.
J
Write 0 in the DSP ICR idle mode configuration register bits for each
subdomain to be restarted.
J
Execute an idle instruction to force the reread of the DSP ICR idle
mode configuration register and restart the subdomain clocks
affected.
Specific conditions must be met for the traffic controller, the system DMA
controller, and the MPU TIPB bridges to enter the idle mode.
To enter idle mode, the traffic controller must meet the following conditions:
-
MPU and DSP must be set to global idle mode.
-
L3 OCP-I is in idle mode. This can be done either by clearing the
EN_OCPI_CK bit of the ARM_IDLECT3 register to 0, or by setting the
IDLOCPI_ARM bit in the same register to 1 (which allows disabling of the
OCPI clock in conjunction with the MPU clock). The OCP initiator bus
enable signal (L3_OCPI_EN) must always be 0 before the OCPI clock
stops.
SPRU749A