Texas Instruments OMAP5912 Reference Manual page 384

Figure 6. LDO005
Table 7. LDO005 Pins
Name Type
VDD Power signal ring
VDDS Power signal ring
VOUT Power signal/pad side
VSS Power signal ring
VSSS Power signal ring
PWRDN Digital signal input
SLEEP Digital signal input
STEADY Digital signal output
SPRU751A
VDD
PWRDN
LDO005
SLEEP
VSS
Description
I/O Positive core power supply
I/O Positive periphery power supply input voltage
Core Positive output voltage connected to DPLL power supply
and bond pad
I/O Core ground
I/O Periphery ground connected to DPLLs ground
Core Powerdown mode when PWRDN is high
Core Control input bypass VDD core voltage to VOUT: active
high
Core Output flag: high when the regulator is active
Figure 7 shows the LDO005 block.
Low-Dropout Voltage Regulator
VDDS
VOUT
STEADY
VSSS
VSSS
Clocks 29