Texas Instruments OMAP5912 Reference Manual page 182

Clock Generation and Reset Management
4 Clock Generation and Reset Management
4.1 Overview
124 OMAP3.2 Subsystem
The clock generation and system reset module is part of the MPU subsystem
in the OMAP 3.2 platform. This module manages the clock generation modes
for the microprocessor unit (MPU), the digital signal processor (DSP), and
various other subsystems (memory interface, system DMA controller, MPU
port interface (MPUI), etc.). These clocks can be controlled by software from
registers described in Section 4.5. It also monitors the system reset and
initiates the reset sequences for each clock domain. Finally, it controls the
power-saving modes and generates wake-up controls to the processors and
peripherals.
Clock generation modes include:
-
Programmable clocking mode (synchronous, synchronous scalable, and
mix modes)
-
Programmable clock for different clock domains (MPU, DSP, and traffic
controller (TC) clock domains)
-
Programmable clock for different peripherals (internal liquid crystal
display (LCD) controller and external MPU and DSP TIPB peripherals)
-
Programmable low-frequency clocks (derived from input reference clock)
to supply the internal MPU and DSP timers
-
Fixed low-frequency clocks to supply watchdog timers for the DSP and
MPU
-
Direct memory access (DMA) clock request mechanism (provides DMA
clock during data transfer only)
-
External visibility on internally generated clocks on POCLKOUT pins
System reset includes:
-
Global software reset
-
Reset control for the MPU, DSP, and external TIPB peripherals
-
System and reset status monitoring
Power-saving modes and wake-up control includes:
-
Programmable power-saving mode and idle mode controls for the MPU,
the DSP, the traffic controller, and their respective subdomains
SPRU749A