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7.3.6
Boot
7.4
Registers
SPRU750A
After reset, the TLB is empty, the MMU is disabled, and the DSP is held in reset.
The fields of LOCK_REG must be initialized from the MPU before enabling the
MMU. TLB entries can then be initialized as needed, starting from entry zero
and incrementing current_victim in LOCK_REG as each entry is written. The
base_value field in LOCK_REG can be set to lock the initialized TLB entries
if the table walker is to be enabled.
If required, the TTB is then programmed and the table walker enabled.
The MMU then can be released from reset and enabled (a single write to
CNTL_REG), and the DSP can be released from reset.
If some TLB entries are not initialized (and the current_victim counter has not
reached 31), the table walker fills the TLB based on misses until current_victim
= 31. The random replacement algorithm is then activated for subsequent
misses. When disabled, the MMU performs no translation and builds the 32-bit
OMAP address, setting bits 31-24 to 0 and bits 23-0 to the DSP byte address.
The DSP MMU registers have the following characteristics:
-
All registers are 32 bits wide
-
Bits marked as unused must be written as zero and return an
unpredictable value when read.
-
The value returned from a read of a bit marked as not readable is
unpredictable.
-
Writes to bits marked as not writable are ignored.
Table 19 lists the DSP MMU registers. Table 21 through Table 41 describe the
register bits.
DSP Memory Management Unit
DSP Subsystem
75
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