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TIPB Bridge
Figure 44.
OMAP 3.2 Platform TI Peripheral Bridge
MPU
System
DMA
controller
L3 OCP-I
port
7.1
Functionality
7.1.1
Bus Allocation
194
OMAP3.2 Subsystem
DMA/OCP-I
arbiter
This section describes the functionality of the TI peripheral bus bridge.
The TIPB is shared between the MPU memory interface, the OCP initiator
(OCP-I), and the DMA controller. Two levels of bus allocation are used to
resolve conflicts and prioritize accesses among the three requestors.
The first level of the two-level arbitration process selects between the DMA
and OCP-I for control of the TIPB. Fixed or round-robin priority schemes can
be programmed in the FIXNROUND_PRIORITY bit field of the TIPB allocation
control register, (RHEA_BUS_ALLOC). When fixed priority is selected, the
EXTNINT_PRIORITY bit field determines whether DMA or OCP-I has fixed
priority.
The second level of the two-level arbitration process selects between the MPU
and the DMA/OCP-I. The value programmed in the RHEA_PRIORITY bits of
(RHEA_BUS_ALLOC) defines the priority. If the value is 0, the MPU memory
interface has priority over the DMA/OCP-I. If the value equals n (where n is
from 1 to 7), the DMA/OCP-I has priority over the MPU and it can perform n
accesses before giving the priority back to MPU memory interface.
TIPB
bridge
(private)
MPU−
DMA/OCP-I
arbiter
TIPB
bridge
(public)
TIPB bridge
configuration registers
TIPB peripherals
32
Private TIPB
32
Public TIPB
TIPB peripherals
SPRU749A
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