Texas Instruments OMAP5912 Reference Manual page 177

Table 51. DLL URD Status Register (EMIFF_DLL_URD_STAT) (Continued)
Bit Field
1 UDF
0 OVF
Table 52. EMIFF SDRAM Register (EMIFF_EMRS2)
Bit Field
31:0 Reserved
Table 53. DLL LRD Control Register (EMIFF_DLL_LRD_CTRL)
Bit Field
31:26 Reserved
25:20 Read offset
19:0 Reserved
3.8 OCPI Registers
SPRU749A
Base Address = 0xFFFE CC00, Offset = 0xC4
Description
Underflow status
0: DLL is OK.
1: DLL counter underflow
Overflow status
0: DLL is OK.
1: DLL counter overflow
This register controls the DLL for the lower read byte.
Base Address = 0xFFFE CC00, Offset = 0xC8
Description
Must be all 0.
This register is provided to anticipate its use in future designs by memory
manufacturers and must not be used by current applications.
A CPU write to this register generates a LOAD MODE register command, with
BA1, BA0 = 1,1. Twelve bits can be loaded.
Base Address = 0xFFFE CC00, Offset = 0xCC
Description
Must be all 0s
6-bit QDS delay fine adjustment, signed, range
– 32...+31. Effective in both DLL enabled and DLL
disable modes. Used for delaying the read dqs for
the lower byte.
One step represents a 26.3 ps ± 10.5 ps delay
adjustment.
Must be all 0s
Table 54 lists the OCP registers. Table 55 through Table 60 describe the
register bits.
Traffic Controller
R/W Reset
R
R
R/W Reset
R/W Reset
R/W
R/W
R/W 0x00000
OMAP3.2 Subsystem
0
0
0x00
0x00
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