Texas Instruments OMAP5912 Reference Manual page 837

Figure 7. Copy-Back Operation
Write 0x70,
NND_COMMAND_SEC
Status = read
NND_ACCESS
Bit 6
= 1
(Ready/Busy_)
?
Yes
Write 0x00,
NND_COMMAND_SEC
Bit 6 is the ready/busy bit
Bit 0 indicates the program
operation has been succesfully
2.1.6 Multiplane Copy-Back Program Operation
SPRU756A
Write source address, NND_ADDR_SRC
Write 0x00, NND_COMMAND
No
Write 0x8A, NND_COMMAND
Write 0x10, NND_COMMAND_SEC
Write 0x70, NND_COMMAND_SEC
dobe
The multiplane copy-back program is an extension of the one-page copy-back
program and is available on 512M-bit and 1G-bit NFMCs (see Figure 8).
First, the command for read operation (0x00) is sent, followed by the source
address. Any further read operation (up to three) for transferring the
addressed pages to the corresponding page register must be executed with
command code 0x03 instead of a 0x00 command. Up to four pages can be
addressed.
There is a latency time Tr (typically 12 µs), indicated by the R/B_ line going low,
between each source address. Data is transferred from memory cells to the
NFMC internal buffer. After the input of commands for reading the source
pages, the same procedure as multiplane page programming occurs, except
that the command operation is 0x8A instead of 0x80. Because no
programming process is involved during data loading at the destination plane
Start copy−back
Wait tr time or interrupt
Write destination address,
NND_ADDRS_SRC
Status = read NND_ACCESS
No
Bit 6 = 1
?
Yes
Yes
Bit 0 = 1
?
No
End copy−back
Memory Interfaces for the EMIFS
Writing to this register, sends also
the address to the flash core.
There is a latency after the address
is sent, for the to be ready.
This can be done by:
− An interrupt
− Reading the NAND flash status
register
− Polling the ready bit in the
NND_READY register of the
NAND flash controller
Writing to this register, also
sends the address to the
flash core
Flash core is busy
programming the data
Program error
Memory Interfaces 31