Texas Instruments OMAP5912 Reference Manual page 699

Table 30. Autoinitialization Bits Summary for LCD Channel in Noncompatible Mode
Auto_init Repeat end_prog Autoinitialization Behavior
Don't
0 Don't care
care
1 0
1 0
1 1 Don't care
3.2.6 DMA_LCD_Disable/Bus Error Feature
SPRU755B
No autoinitialization.
It waits until enable = 1 to enable the LCD logical channel, and loads the
physical LCD channel with its programming register set. However, the LCD
logical channel is active only when the LCD controller enables it.
As both repeat and end_prog bits equal 0, the channel is still enabled but
pending. At the end of the current transfer, the logical LCD channel waits
0 until repeat or end_prog = 1 to reactivate itself again. When end_prog = 1
the programming register set is copied to the active register set: a new
context is programmed.
At the end of the current transfer, the logical LCD channel immediately loads
the physical LCD channel with its programming register set, when physical
1 LCD channel is granted (end_prog = 1 allows loading the new context,
disregarding the repeat bit). The channel reinitializes itself and starts a new
transfer with the new context.
The channel reinitializes itself at the end of the current transfer and starts a
new transfer with the previous context (active register set).
Software can disable the LCD channel on the fly. If the LCD channel is
disabled, then transfer stops immediately.
During LCD channel transfer, if an underflow occurs, the DMA LCD channel
resets its enable bit and the LCD channel stops immediately.
LCD PCh underflow is possible when the destination is the OMAP LCD
controller (reads from external controller are stalled until data is ready).
If underflow occurs, a signal is sent to the OMAP LCD controller, and the FUF
bit is set in the OMAP LCD controller status register (LCSR). An interrupt is
generated when a LCSR bit is set. See the Multimedia Processor Display
Interface Reference Guide (SPRU764).
If one hardware request is currently being serviced, and other hardware
requests are triggered, then the DMA_LCD controller will stop and signal an
event drop interrupt on the second new hardware request (bus error).
Direct Memory Access (DMA) Support
System DMA
75