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Power Management User Services
Table 43. Idle Configuration Register (ICR) (Continued)
MPU Base Address (byte) = 0xE100 0000, DSP Base Address (word) = 0x00 0000, Offset = 0x01 (word)
Bit
Name
6
RSV
5
EMIF
4
DPLL
3
PER
2
CACHE
1
DMA
0
CPU
Note:
The R/W values indicate DSP access only. MPU access is read only.
Table 44. Idle Status Register (ISTR)
MPU Base Address (byte) = 0xE100 0000, DSP Base Address (word) = 0x00 0000, Offset = 0x02 (word)
Bit
Name
15:8
Reserved
7
RHEA_IDLE7_TR
6
RHEA_IDLE6_TR
5
RHEA_IDLEEMIF_TR
4
RHEA_IDLEDPLL_TR
3
RHEA_IDLEPERH_TR
76
Power Management
Function
Reserved idle domain.
EMIF idle domain.
DPLL idle domain.
PER idle domain.
CACHE idle domain.
DMA idle domain.
CPU idle domain.
This register defines six domains:
-
CPU
-
DMA
-
ICache
-
Peripherals
-
Clock generator (DPLL)
-
EMIF
To put one or more domains in idle mode, the user must set the corresponding
bits in this register to 1 and then execute the DSP idle instruction.
A second register, the idle status register (ISTR), also located in the TIP bridge,
reflects the state of the DSP when the idle instruction is executed. Table 44
defines ISTR.
Function
Reserved
Reserved idle status
Reserved idle status
EMIF idle status
DPLL idle status.
PER idle status.
R/W *
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Reset
R
0
R
0
R
0
R
0
R
0
R
0
SPRU753A
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