Texas Instruments OMAP5912 Reference Manual page 409

OMAP5912 Clock Architecture
Table 15. Active Clocks in Big Sleep Mode (Continued)
Module/ Clock Description
OMAP5912 I/O
Destination
USB OTG EXT_48M
48 MHz from ULPD
MMC/SDIO1 EXT_48M
48 MHz from ULPD
MMC/SDIO2 EXT_48M
48 MHz from ULPD
Notes: 1) The frequency on the BCLK can be set accordingly: SDW_CLK_DIV_CTRL_SEL[7:2]. The resulting frequency is
given in the following table:
SDW_CLK_DIV_CTRL_SEL[7:2] = 0X00000, BCLK = 48 MHz
SDW_CLK_DIV_CTRL_SEL[7:2] = 0X00001, BCLK = 32 MHz
SDW_CLK_DIV_CTRL_SEL[7:2] = 0X00002, BCLK = 24 MHz
SDW_CLK_DIV_CTRL_SEL[7:2] = 0X00003, BCLK = 19.2 MHz
SDW_CLK_DIV_CTRL_SEL[7:2] = 0X00004, BCLK = 16 MHz
SDW_CLK_DIV_CTRL_SEL[7:2] = 0X00005, BCLK = 13.7 MHz
SDW_CLK_DIV_CTRL_SEL[7:2] = 0X00006, BCLK = 12 MHz
SDW_CLK_DIV_CTRL_SEL[7:2] = 0X00007, BCLK = 9.6 MHz
SDW_CLK_DIV_CTRL_SEL[7:2] = 0X00008, BCLK = 8 MHz
SDW_CLK_DIV_CTRL_SEL[7:2] = 0X00009, BCLK = 6.9 MHz
SDW_CLK_DIV_CTRL_SEL[7:2] = 0X000012, BCLK = 3 MHz
SDW_CLK_DIV_CTRL_SEL[7:2] = 0X000032, BCLK = 1 MHz
54 Clocks
Active Request
USB_DPLL_MCLK_REQ
CONF_MOD_USB_HOST_
HHC_UHOST_EN_R
SOFT_REQ_REG[8]
MOD_CONF_CTRL_0[23]
SOFT_REQ_REG[12]
MOD_CONF_CTRL_0[20]
SOFT_REQ_REG[13]
Notes
SPRU751A