Texas Instruments OMAP5912 Reference Manual page 136

Traffic Controller
3.3.2 Initialization Sequence
78 OMAP3.2 Subsystem
Before it can be accessed for writing or reading after power on, or when exiting
deep power-down mode, an SDRAM device must be initialized with various
protocol parameters (burst size, CAS idle time, write burst, etc.). This is known
in SDRAM literature as the initialization sequence.
Because SDR SDRAM and DDR SDRAM require different initialization
sequences, the sequence is manually software driven, using the EMIFF
SDRAM manual command register (writing a command opcode into that
register, generates that command on the SDRAM interface).
The SDRAM operations register should only be programmed after the "a
precharge all command" has been issued.
For SDR SDRAM devices, the initialization of the SDRAM bank is
accomplished via a preprogrammed series of writes to the command register
and the MRS register. There are two possibilities to generate the initialization
sequence:
-
Writing to the EMIFF SDRAM MRS register (legacy) in the SDRAM
controller sets up the device to interface with OMAP. The following
SDRAM command sequence is automatically generated:
1) Precharge all
2) Load mode register
3) Autorefresh
The EMIFF SDRAM MRS register (legacy) is provided for compatibility
with existing code and must not be used by new software drivers.
-
The new recommended procedure is:
1) Wait for 200 µs after power up and memory clock is running and
stable. The software is responsible for this initial wait. During this wait,
NOP commands are the default commands automatically sent to the
memory.
2) Apply a PRECHARGE ALL command. This is accomplished by writing
to the command register.
3) Apply two AUTOREFRESH commands. This is accomplished by two
consecutive writes to the command register.
4) Apply an MRS LOAD command. This is accomplished by writing to the
EMIFF SDRAM MRS register (new) (uses the new address, not the
legacy address).
SPRU749A