Texas Instruments OMAP5912 Reference Manual page 542

Ultralow-Power Device
Figure 6. Simplified State Diagram of the ULPD FSM1
AWAKE
Wake-up request from
OMAP or UART2 request
for system clock
or power up context
No external clock request.
Idle request from OMAP and
[DEEP_SLEEP_TRANSITION_EN]
Table 1. Sleep Modes versus Active Mode (Summary)
Mode Power Dissipation
Deep sleep Lowest
Big sleep From modules
clocked by active
32-kHz or 48-MHz
clocks
Awake Nominal
24 Power Management
Wake-up request from
OMAP or UART2 request
for system clock
Idle request from OMAP
and external clock
request or not
POWER_CTRL_REG
[DEEP_SLEEP_
TRANSITION_EN]
DEEP SLEEP
The ULPD handles the state transitions among deep sleep, big sleep, and
awake. The transitions are triggered by the following:
-
External events: Hardware resets or clock requests
-
Internal events: Software resets, watchdog time-out, software clock
request, or MPU idle request
Active Clocks
32 kHz for wake-up
detection
System and 32-kHz
clock. ULDP output
clocks to peripherals if
requested
All 32-kHz, 48-MHz, and
clocks derived from
system clock can be
active.
BIG SLEEP
No external clock request.
No wake-up request from OMAP
and POWER_CTRL_REG
[DEEP_SLEEP_
TRANSITION_EN]
External clock
request
Comments
Only the UART2 functional clock using
32 kHz is active.
For BCLK and MCLK, the 48-MHz
frequency can be divided further by
setting respectively
SDW_CLK_DIV_CTRL_SEL[7:2] and
COM_RATIO_SEL[7:2] in ULPD control
registers.
OMAP3.2 input clock is active.
SPRU753A