Texas Instruments OMAP5912 Reference Manual page 651

Multimedia processor device overview and architecture
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Table 14. Functional Multiplexing DSP DMA C Register (FUNC_MUX_DSP_DMA_C
Bit
Name
31:30
RESERVED
29:25
CONF_DSP_DMA_REQ_18
24:20
CONF_DSP_DMA_REQ_17
19:15
CONF_DSP_DMA_REQ_16
14:10
CONF_DSP_DMA_REQ_15
9:5
CONF_DSP_DMA_REQ_14
4:0
CONF_DSP_DMA_REQ_13
Table 15. Functional Multiplexing DSP DMA D Register (FUNC_MUX_DSP_DMA_D)
Bit
Name
31:5
RESERVED
4:0
CONF_DSP_DMA_REQ_19
SPRU755B
Base Address = 0xFFFE 1000, Offset Address = 0xD8
Function
Reserved
Writing value n in this register maps DMA
request source n+1 to DSP DMA controller
DMA_REQ(18). n is between 0 and 27
Writing value n in this register maps DMA
request source n+1 to DSP DMA controller
DMA_REQ(17). n is between 0 and 27
Writing value n in this register maps DMA
request source n+1 to DSP DMA controller
DMA_REQ(16). n is between 0 and 27
Writing value n in this register maps DMA
request source n+1 to DSP DMA controller
DMA_REQ(15). n is between 0 and 27
Writing value n in this register maps DMA
request source n+1 to DSP DMA controller
DMA_REQ(14). n is between 0 and 27
Writing value n in this register maps DMA
request source n+1 to DSP DMA controller
DMA_REQ(13). n is between 0 and 27
Base Address = 0xFFFE 1000, Offset Address = 0xDC
Function
Reserved for future expansion
Writing value n in this register maps DMA
request source n+1 to DSP DMA controller
DMA_REQ(19). n is between 0 and 27
.
.
.
.
.
.
.
Direct Memory Access (DMA) Support
GDMA Handlers
R/W
Reset
R/W
0x0
R/W
0x11
R/W
0x10
R/W
0x0F
R/W
0x0E
R/W
0x0D
R/W
0x0C
R/W
Reset
R/W
0x0000000
R/W
0x12
27

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