Texas Instruments OMAP5912 Reference Manual page 882

Software NAND Flash Controller
Step 2: Read Data From NAND Flash Device
76 Memory Interfaces
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The MPU programs the system DMA:
J
Transfer the data in 8-,16-, or 32-bit word format from
theNAND_FLASH device to SDRAM.
J
Transfer mode (single mode= > channel stop when current transfer
finishes)
J
The DMA creates an interrupt on completion of the transfer.
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The processor MPU configures the NAND flash controller peripheral as
follows:
J
Selects the number of blocks to calculate ECC on (1-9) the
NND_ECC_SELECT register
J
Selects the type of ECC (256/512 byte blocks) by programming the
NND_CTRL register
J
Enables the read and program operation: ECC logic-enable by
programming bit 0 of the NND_CTRL register
J
Enables the clock in the NND_SYSCFG register bit 0
J
Configures NAND flash FIFO access (NND_CTRL)
J
Sets 1 in NND_PSC_CLK (the module runs full speed for minimum
delay in the ECC calculation)
J
Resets ECC calculation by writing to NND_RESET
Note:
To optimize the transfer from SDRAM to the NAND flash controller, keep the
RDY/BUSY signal of the NAND flash controller at 1.
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The processor initiates a read command.
-
The R/B signal goes low to signify that the NAND flash is busy with the
internal programming operation (t
-
The R/B signal goes high, creating an interrupt to the processor that
signifies that the NAND flash device is ready to send data.
-
The MPU programs the system DMA:
J
Transfer start ( software request)
-
Data are transmitted from the NAND flash device to SDRAM.
-
The DMA interrupts the processor when the transfer is complete:
J
The calcuation of ECC can begin.
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PROG
SPRU756A