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Clock Generation and Reset Management
4.2.3
MPU Clock Domain
130
OMAP3.2 Subsystem
in bypass mode and switches to locked clock in an other 32 maximum
reference clock cycles. If the DPLL was synthesizing a frequency prior to the
idle state, the DPLL switches from bypass mode to synthesizer frequency
when the lock state is reacquired.
The DPLL1 output frequency defines the speed of the MPU and the MPU
external peripherals. The clock from DPLL1 output is supplied to the OMAP
boundary.
It
has
(IDL_CLKOUT_ARM) and in ARM_IDLECT2 (EN_CKOUT_ARM).
At reset, DPLL1 is in bypass mode (CK_GEN1 = CK_REF).
The MPU clock domain is subdivided into five subdomains.
-
MPU (ARM_CK)
You can program the divide-down ARMDIV bits of the ARM_CKCTL
register to have the DPLL1 output clock (CK_GEN1) further divided by 1,
2, 4, or 8 to supply the clock signal driving the MPU. At reset, the highest
frequency (divided by 1) is selected: ARM_CK = CK_GEN1 = CK_REF.
-
MPU external peripheral (ARMPER_CK or ARMXOR_CK)
You can program the divide-down PERDIV bits of the ARM_CKCTL regis-
ter to have CK_GEN1 further divided by 1, 2, 4, or 8 to supply the MPU
external peripheral clock ARMPER_CK signal at the OMAP boundary. At
reset, the highest frequency (divided by 1) is selected and ARMPER_CK
is active. ARMXOR_CK, a gated version of CK_REF, can also be used to
supply the external peripherals. At reset, this clock is inactive.
-
OMAP3.2 MPU internal OS timers (ARMTIM_CK)
The ARM_TIMXO bit of the ARM_CKCTL register selects either
CK_GEN1 divided by 1 or the input reference clock (CK_REF) to supply
the internal MPU timers. At reset, CK_GEN1 is selected but the timer clock
is inactive.
-
MPU Level 1 and 2 interrupt handlers (ARM_INTH_CK)
The MPU interrupt handlers are supplied by a programmable clock, and
the user can choose between the MPU clock or the divided-by-2 MPU
clock using the ARM_INTHCK_SEL bit of the ARM_CKCTL register. The
MPU clock is supplied as the default clock.
-
32-bit MPU watchdog timer (ARMWDI_CK)
The 32-bit MPU watchdog timer is supplied with a low-frequency clock
(CK_REF/14). This clock is active at reset.
a
software
gating
in
the
ARM_IDLECT1
SPRU749A
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