Texas Instruments OMAP5912 Reference Manual page 584

Ultralow-Power Device
Table 37. COM Clock Divider Control Select Register (COM_CLK_DIV_CTRL_SEL)
(Continued)
Bit Name
1 COM_ULPD_PLL_CLK_REQ
0 COM_SYSCLK_PLLCLK_SEL
Table 38. CAM Clock Control Register (CAM_CLK_CTRL)
Bit Name
15:3 UNUSED
2 SYSTEM_CLK_EN
1 CAM_CLK_DIV
0 CAM_CLOCK_EN
Table 39. Software Request Register2 (SOFT_REQ_REG2)
Bit Name
15:1 UNUSED
0 SOFT_CLOCK3_DPLL_REQ
66 Power Management
Base Address = 0xFFFE 0800, Offset = 0x78
Function
MCLK clock software request
0: Request inactive
1: Request active
0: Select the divided version of APLL output
clock for MCLK
1: Select SYSTEM_CLOCK for MCLK or 48
MHz
Base Address = 0xFFFE 0800, Offset = 0x7C
Function
Unused
Clock enable of the system clock for GPIO modules
0: Clock disabled
1: Clock enabled
When 0, the CAM.CLKOUT is the system clock.
When 1, the CAM.CLKOUT is the system clock.
Enable of the CAM.CLKOUT.
When 0, the CAM.CLKOUT is off.
When 1, the CAM.CLKOUT is on.
Base Address = 0xFFFE 0800, Offset = 0x80
Function
Unused
PLL software request reserved for future
use.
1: Request active
0: Request inactive
R/W Reset
R/W 0x0
R/W 0x1
R/W Reset
R 0x0
R/W 0x0
R/W 0x0
R/W 0x0
R/W Reset
R 0x0
R/W 0X0
SPRU753A