Texas Instruments OMAP5912 Reference Manual page 175

Table 47. EMIFF Abort Address Register (EMIFF_AADDR)
Bit Field
31:0 Abort Address
Table 48. EMIFF Abort Type Register (EMIFF_ATYPER)
Bit Field
31:3 Reserved
2:1 HOSTID
0 ABORT_FLAG
Table 49. DLL LRD Status Register (EMIFF_DLL_LRD_STAT)
Bit Field
31:0 Reserved
Table 50. DLL URD Control Register (EMIFF_DLL_URD_CTRL)
Bit Field
31:26 Reserved
25:20 Read offset
19:16 Reserved
SPRU749A
Base Address = 0xFFFE CC00, Offset = 0x98
Description
Address of the transaction aborted
Base Address = 0xFFFE CC00, Offset = 0x9C
Description
Must be all 0s
ID of the host whose transaction was aborted
00: MPU
01: DSP
10: DMA
11: OCP-I
Set when an abort occurs, reset when this register is
read.
Base Address = 0xFFFE CC00, Offset = 0xBC
Description
Must be all 0s.
Base Address = 0xFFFE CC00, Offset = 0xC0
Description
Must be all 0s
6-bit QDS delay fine adjustment, signed, range
– 32...+31. Effective in both DLL enabled and DLL
disabled mode. Used for delaying the read dqs for
the upper byte.
One step represents a 26.3 ps ± 10.5 ps delay
adjustment.
Must be all 0s
Traffic Controller
R/W Reset
R 0x00000000
R/W Reset
R 0x0000000
R
R
R/W Reset
R 0x00000000
R/W Reset
R
R/W
R
OMAP3.2 Subsystem
00
0
0x00
0x00
0x0
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