Texas Instruments OMAP5912 Reference Manual page 583

Table 36. SDW Clock Divider Control Select Register (SDW_CLK_DIV_CTRL_SEL)
Bit Name
15:8 UNUSED
7:2 SDW_RATIO_SEL
1 SDW_ULPD_PLL_CLK_REQ
0 SDW_SYSCLK_PLLCLK_SEL
Table 37. COM Clock Divider Control Select Register (COM_CLK_DIV_CTRL_SEL)
Bit Name
15:8 UNUSED
7:2 COM_RATIO_SEL
SPRU753A
Base Address = 0xFFFE 0800, Offset = 0x74
Function
Unused
Select the divider ratio to apply to the APLL
output clock to generate BCLK.
000000=>1; 000001=>1.5; 000010=>2;
000011=>2.5
000100=>3; 000101=>3.5; 000110=>4;
000111=>5;
001000=>6; 001001=>7; .... 010010=>16 ...
110010=>48.
BCLK clock software request.
0: Request inactive
1: Request active
0: Select the divided version of APLL output
clock for BCLK
1: Select SYSTEM_CLOCK for BCLK
Base Address = 0xFFFE 0800, Offset = 0x78
Function
Unused
Select the divider ratio to apply to the APLL
output clock to generate MCLK.
000000=> 1
000001=>1.5;
000010=>2;
000011=>2.5
000100=> 3;
000101=>3.5
000110=>4;
000111=>5
001000=>6
001001=>7
010010=>16
110010=>48
Ultralow-Power Device
R/W
R
R/W
R/W
R/W
R/W
R
R/W
Power Management
Reset
0x0
0x0
0x0
0x1
Reset
0x0
0x0
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