Texas Instruments OMAP5912 Reference Manual page 180

Traffic Controller
Table 60. Secure Mode Register (OCPI_SMR)
Bit Name
31:7 Reserved
6 API
5 RHEA_PRIV
4 OCPMult
3 OCPT2
2 OCPT1
1 EMIFF
0 EMIFS
122 OMAP3.2 Subsystem
Base Address = 0xFFFE C320, Offset = 0x18
Function
Reserved. Must be 0.
In secure mode
0: Access is allowed.
1: Access to API is prohibited from initiator.
In secure mode
0: Access is allowed.
1: Access to MPU TIPB public is prohibited from
initiator. TIPB private bus is not accessible regardless
of the setting of this bit.
In secure mode
0: Access is allowed.
1: Access to OCP multibank is prohibited from initiator.
In secure mode
0: Access is allowed.
1: Access to OCPT2 is prohibited from initiator.
In secure mode
0: Access is allowed.
1: Access to OCPT1 is prohibited from initiator.
In secure mode
0: Access is allowed.
1: Access to EMIFF is prohibited from initiator.
In secure mode
0: Access is allowed to CS1−CS3.
1: Access to EMIFS CS1−CS3 is prohibited from
initiator; CS0 is not accessible regardless of the setting
of this bit.
When not in secure mode, these secure mode register values are ignored.
When in secure mode, EMIFS CS0 and TIPB private access is not allowed,
regardless of the register values. Every other target secure mode is
determined by the register value.
R/W Reset
R/W 0
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
SPRU749A