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Single-Indexed Addressing Mode
SPRU755B
When block 1 is active:
A(0) = TB1.
A(n+1) = A(n) + ES_B1 until the end of block 1.
Then, when A(n) reaches BB1, A(n+1) = TB2: block 2 becomes active.
When block 2 is active:
A(n) = TB2.
A(n+1) = A(n) + ES_B2 until the end of block 2.
Then, when A(n) reaches BB2, A(n+1) = TB1: block 1 becomes active
again.
Address is incremented by element size and element index. All is ex-
pressed in bytes.
DBM = 0 (one block mode)
Only block 1 is active:
A(0) = TB1.
A(n+1) = A(n) + ES_B1 + (EI_B1 – 1)
where EI_B1 = ((Stride_EI_B1 – 1) * ES_B1) + 1
A(n) is incremented in this way until the end of block 1. Then, when A(n)
reaches BB1, A(n+1) = TB1 again.
Note:
Stride_EI_B1 = 1 (equivalent to EI_B1 = 1) gives consecutive element ac-
cesses, hence the same behavior as with the post-incremented addressing
mode.
DBM = 1 (dual block mode)
When block 1 is active:
A(0) = TB1.
A(n+1) = A(n) + ES_B1 + (EI_B1 – 1)
where EI_B1 = ((Stride_EI_B1 – 1) * ES_B1) + 1
A(n) is incremented in this way until the end of block 1. Then, when A(n)
reaches BB1, A(n+1) = TB2: block 2 becomes active.
When block 2 is active:
A(n) = TB2.
A(n+1) = A(n) + ES_B2 + (EI_B2 – 1)
where EI_B2 = ((Stride_EI_B2 – 1) * ES_B2) + 1
Direct Memory Access (DMA) Support
System DMA
71
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