Texas Instruments OMAP5912 Reference Manual page 354

A
Architecture, C55x DSP 21
Architecture overview 15
C
Cache functional configuration 33
D
DSP cache memory 24
DSP clocking and reset 83
DSP components
DSP module 17
DSP subsystem peripherals 17
DSP core 17
DSP CPU 18
hardware acceleration 20
on chip memory 19
overview 20
DSP CPU overview 20
DSP EMIF global control register 57
DSP EMIF global reset register 58
DSP external memory interface 57
EMIF global control register 57
EMIF global reset register 58
DSP hardware acceleration 20
DSP instruction cache 23
cache memory organization 24
ramset memory organization 25
ramset structure 27
structure 25
DSP instruction cache configuration 28
DSP instruction cache configuration examples 34
DSP instruction cache emulation mode 38
SPRU750A
DSP instruction cache memory map 39
DSP instruction cache operations 33
cache functional configuration 33
enable and disable 33
freeze mode 34
ramset functional configuration 33
DSP instruction cache performance 37
DSP instruction cache peripheral register
addresses 43
DSP instruction cache structure 25
DSP instruction cache system memory 38
DSP internal memory 23
DSP memory 22
configuration examples 34
emulation mode 38
instruction cache 23
instruction cache configuration 28
instruction cache operations 33
instruction cache performance 37
internal 23
memory map 39
peripheral register addresses 43
system memory 38
DSP memory management unit 58
DSP module 17
DSP MPU interface 54
HOM/SAM 56
ST3−HOM_P 56
ST3−HOM_R 56
DSP private peripherals 83
DSP public peripherals 84
DSP ramset memory 25
DSP ramset structure 27
cache operation 27
DSP subsystem
architecture overview 15
clocking and reset 83
components 17
Index
Index
OMAP5912 91