Texas Instruments OMAP5912 Reference Manual page 131

Multimedia processor device overview and architecture

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Idle Time Between Different Bus Access Transitions (BTMODE = 1)

Wait States During a Write-to-Write and Write-to-Read Transition to Same

Chip-Select (BTWST CSX = 3 BTMODE = 1)

DATA FROM FLASH

DATA TO FLASH

FL_DIR_O(DATAEN)

External Device Reset Control

RD(csy) x != y

WR(csy) x != y

RD(csy)x != y

WR(csy)x !=y

EMIFS interface includes the FLASH.RP output signal. The FLASH.RP

output pin is activated during OMAP warm and cold reset. FLASH.RP is

also activated when the TC enters the idle state if the RESPWR_EN bit

field of the clock and reset ARM_EWUPCT configuration register is set

(See Table 66).

Not inserted

Not inserted

Traffic Controller

Length(BTWST)

OMAP3.2 Subsystem

Chapters

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