Table of Contents
Advertisement
SPRU751A
The cell has level shifters on all input ports to avoid through-current when V
and V
are not at the same voltage. Natural level shifting is done at the cell
DDA
outputs to provide V
DDA
Three modes of operation and one power-down mode can be selected from
the core inputs:
-
Application mode 0: The input frequency is 19.2 MHz, and the
multiplication factor is 5.
-
Application mode 2: The input frequency is 13 MHz, and the multiplication
factor is 96/13.
-
Application mode 3: The input frequency is 12 MHz, and the multiplication
factor is 8.
-
Power-down mode: Tests I
power when the multiplied output clock is not required.
Because the core voltage can vary while V
power-down mode if the voltage on V
Note:
OMAP5912 supports only the above application modes. Although other ap-
plication modes are possible because of the generic nature of APLL, they are
not included in the ULPD architecture.
-compatible CMOS levels.
on the analog power supply and saves
DDQ
DDA
is lower than 200 mV.
DD
Analog Phase-Locked Loop
is stable at 1.8 V, the cell is in
Clocks
DD
17
Advertisement
Chapters
Table of Contents
