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System DMA
34
Direct Memory Access (DMA) Support
Each time a DMA request is received for a synchronized channel, the logical
channel is activated and a block of data is transferred when a physical channel
is assigned to it. This block of data can be:
An element
-
A complete element, which is defined by Data_type. For example, 8/16/32
bits are transferred in response to a DMA request.
An entire frame
-
A complete frame of several elements is transferred in response to a DMA
request.
An entire block
-
A complete block of several frames is transferred in response to a DMA
request.
One DMA request can trigger several logical channels at the same time.
To configure an LCh to synchronize by element, frame, or block, program the
frame synchronization (FS) bit in the DMA_CCR register and the block
synchronization (BS) bit in the DMA_CCR2 register. If both bits are set to 0,
the channel is synchronized by element. Setting both bits to 1 causes
undefined effects.
To configure an LCh to transfer one element per DMA request:
-
1) Configure the data type, also referenced as element size (ES), in the
field Data_type in the channel source destination parameter register
(DMA_CSDP).
2) Configure the number of transfers (elements) to take place before the
LCh gets disabled again in the channel element number register
(DMA_CEN).
3) Configure both FS and BS to 0.
To configure an LCh to transfer one frame per DMA request:
-
1) Configure the element size as described above.
2) Configure the element number as described above. This represents
the number of elements sent per frame, hence per DMA request.
3) Configure the number of transfers (frames) to take place before the
LCh gets disabled again in the channel frame number registers
(DMA_CFN).
4) Configure FS to 1 and BS to 0.
SPRU755B
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