Texas Instruments OMAP5912 Reference Manual page 373

Analog Phase-Locked Loop
Figure 2. APLL Block Diagram
SEL2
LS
LS
PWRDN
LS
CLKIN
LS
SEL[0:1]
LS
TEST
Table 4. Mode Selection Table
PWRDN TEST SEL2
L - -
H L L
H L L
H L L
Note: Full IDDQ mode is reached when the input clock is not toggling; otherwise, a residual current may be found.
18 Clocks
Charge
PFD
pump
Lock detection
CKF
0
1
-
LS: Level shifter
-
LSn: Natural level shifter or two successive buffers tied to different supply
domains. The usual level-shifting scheme is not suited to the clock output
for speed and duty-cycle reasons.
-
MISR: Multiple input-shift register for digital test purposes
SEL1 SEL0 CLKIN
(MHz)
- - 0
L L 19.2
H L 13
H H 12
VCTL
Loop
VCO
filter
Prescaler
ratio: 5, 6, 7 or 8
1 0
Fractional
accumulatior
MISR
CLKOUT SYNC
(MHz)
- -
96 H
96 Pulsed
(1MHz)
96 H
LSn
LOCK
0
LSn
CLKOUT
1
0
LSn
SYNC
1
MODE
(1)
Power down
Application mode 0
Application mode 2
Application mode 3
SPRU751A