Texas Instruments OMAP5912 Reference Manual page 192

Clock Generation and Reset Management
4.3.2 DSP Idle Control
134 OMAP3.2 Subsystem
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The ARM_CK is stopped in a low static state after some
synchronization cycles.
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If the IDLCLKOUT_ARM bit field of ARM_IDLECT1 is set to 1, then the
DPLL output clock also goes to idle after some synchronization
cycles.
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If the IDLPER_ARM bit field of ARM_IDLECT1 is set to 1, then the
ARMPER_CK also goes to idle if the ARMPER_IDLE_REQ request is
acknowledged.
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If the IDLXOR_ARM bit field of ARM_IDLECT1 is set to 1, then the
ARMXOR_CK also goes to idle after some synchronization cycles.
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If the IDLWDT_ARM bit field of ARM_IDLECT1 is set to 1, then the
ARMWDT_CK also goes to idle after some synchronization cycles, if
the MPU watchdog module is not set.
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If the IDLTIM_ARM bit field of ARM_IDLECT1 is set to 1, then the
ARMTIM_CK also goes to idle after some synchronization cycles.
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If the IDLAPI_ARM bit field of ARM_IDLECT1 is set to 1, then the
MPUI clock also goes to idle whenever the MPUI is not required.
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If the IDLDPLL_ARM bit field of ARM_IDLECT1 is set to 1, then the
DPLL macro goes to idle when all the clock domains are in idle.
Even when the MPU is not in idle mode, the user has the option of individually
disabling the MPU subdomain clocks by setting the corresponding bit in the
ARM_IDLECT2.
A wake-up sequence is initiated in the MPU domain only upon:
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A system reset
or
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An unmasked MPU interrupt request, assuming that the
WKUP_MODE bit of ARM_IDLECT1 is set to 1 or the chip is not in idle.
In case of chip idle and WKUP_MODE set to 0, the external wake-up
control feature is enabled and a CHIP_nWKUP low along with the
interrupt is needed to wake-up the MPU.
On wake-up, all the subdomains put in idle mode using ARM_IDLECT1 are
restarted if the corresponding enable bits of ARM_IDLECT2 are set.
The DSP idle instruction must be executed in host-only mode (HOM) to initiate
the DSP idle mode. Depending on the settings of the DSP idle control registers
SPRU749A