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Step 3: Calculate ECC
Step 4: Postprocessing
SPRU756A
-
The R/B signal goes low to signify that the NAND flash is busy with the
internal operation.
-
The R/B signal goes high, creating an interrupt to the processor that
signifies that the block read has been completed (new block can be read).
-
The MPU programs the system DMA:
J
Transfer the data in 8-, 16-, or 32-bit word format from SDRAM into the
NAND flash controller.
J
Transfer mode (single mode= > channel stop when current transfer
finishes)
J
The DMA creates an interrupt on completion of the transfer.
J
Transfer start (hardware start => on DMA request)
-
The processor initiates a write command to the NAND flash device (in the
NAND flash controller) NND_COMMAND.
-
The data is written into the NAND flash controller peripheral by the DMA
in FIFO.
-
ECC is calculated.
-
The DMA interrupts the processor when the transfer is complete.
-
The processor reads the ECC calculation from the NAND flash controller
peripheral.
-
The processor checks the ECC result with the one save in SDRAM (spare
area)
Figure 22 shows the interface between the OMAP161X and a NAND flash
device.
Software NAND Flash Controller
Memory Interfaces
77
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