Texas Instruments OMAP5912 Reference Manual page 433

Multimedia processor device overview and architecture

Hide thumbs Also See for OMAP5912:

Table of Contents

Reset Architecture

Reset Distribution to Peripherals

PWRON_RESET_CORE

Initialization

Sync counter

Class 1 Modules

CHIP_RESET_IN

RTC power split

Note that in Figure 1, peripheral classes group peripherals based on the

source of the reset input.

The ULPD is in charge of generating two functional reset signals to the MPU

subsystem (OMAP3.2 core): cold reset (PIPORN) and warm reset

(PICHIPNRST). It is then the task of the MPU subsystem to reset processors

and peripherals. In addition, there are three input resets to the ULPD. Two of

these resets are external pins: PWRON_RESET (cold reset on ball R12) and

MPU_RST (warm reset on ball U20). The 32-kHz watchdog timer reset is a

Class 2 Modules

Class 3 Modules

Class 2 Modules

Compact flash

32K Watchdog

interconnect

MC U L2 INTH

MOD_CONF_CTRL_1[23]

Chapters

Table of Contents