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I2C Multimaster Peripheral
Table 15. Signal Pads
Name
Type
I2C_SCL
In/
Out(OD)
I2C_SDA
In/
Out(OD)
2.5
Operational Details
2
2.5.1
I
C Reset
Table 16. Reset State of I
Pin
I/O/Z
SDA
I/O/Z
SCL
I/O/Z
2
2.5.2
I
C Bit Transfer
58
Serial Interfaces
Reset
Description
Value
2
Input
I
C serial CLK line.
Open-drain output buffer. Requires external pull-up resistor (Rp).
2
Input
I
C serial data line.
Open-drain output buffer. Requires external pull-up resistor (Rp).
2
The I
C module can be reset in the following three ways:
A system bus reset (RESET_ = 0). A device reset causes the system bus
-
reset.
A software reset by setting the SRST bit in the I2C_SYSC register. This
-
bit has the same action on the module logic as the system bus reset.
The I2C_EN bit in the I2C_CON register can also reset a part of the I
-
module. When the system bus reset is released (RESET_ = 1), I2C_EN
= 0 keeps the functional part of the I
configuration registers can be accessed.
2
C Signals
System Reset
High impedance
High impedance
The master device generates one clock pulse for each data bit transferred.
Because of the variety of technology devices (CMOS, NMOS, bipolar) that can
be connected to the I
not fixed and depend on the associated level of VDD. See Table 17 for
electrical specifications.
2
C module in reset state and all
2
I
C Reset (I2C_EN = 0)
High impedance
High impedance
2
C bus, the levels of logical 0 (low) and 1 (high) are
2
C
SPRU760B
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