Texas Instruments OMAP5912 Reference Manual page 318

Multimedia processor device overview and architecture
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SPRU750A
The MPU domain (including ARM926EJS and system DMA) always masters
the transfer operation. It initiates the read or write of DSP memory or
peripherals. The MPU also controls the parameters of the MPUI by configuring
the MPUI_CTRL_REG and the MPUI_DSP_MPUI_CONFIG register. There
are five additional registers the MPU can read to observe the state of the MPUI:
-
MPUI_DEBUG_ADDR
-
MPUI_DEBUG_DATA
-
MPUI_DEBUG_FLAG
-
MPUI_STATUS_REG
-
MPUI_DSP_STATUS_REG
The MPUI port supports four access modes:
-
Single-access mode, memory (SAM_M): SARAM, DARAM and, external
memory interface are shared between the DSP domain and the MPU
domain.
-
Single-access mode, peripheral (SAM_P): DSP public peripheral bus is
shared between the DSP domain and the MPU domain.
-
Host-only mode, memory (HOM_M): MPU has exclusive access to DSP
SARAM, but it cannot access other DSP memory resources.
-
Host-only mode, peripheral (HOM_P): MPU has exclusive access to the
DSP public peripheral bus.
SAM is the normal operating mode in which all the DSP internal memory and
the public peripherals are accessible by the MPUI interface as well as the DSP.
If both the DSP and the MPU controllers (ARM926EJS and/or system DMA)
access the same memory at the same time, priority is given to the DSP
controllers. The MPU domain access in SAM is synchronized to the internal
DSP CPU clock, which can add access latency for the MPU transfers.
HOM provides the MPU with exclusive access to the DSP SARAM or public
peripherals, primarily to support high-speed transfers from/to DSP during DSP
reset or IDLE conditions. During DSP reset condition, HOM_M and HOM_P
are invoked. In HOM_M the MPUI interface does not have access to the
DARAM (0x000000 −0x00FFFF), but it has access to all the SARAM
(0x010000 −0x050000). The MPU must configure the MPUI_DSP_MPUI
CONFIG register to specify which blocks of SARAM are accessible in HOM
before access, because the reset default is for no SARAM access during
HOM_M.
An additional condition is that in HOM_P only the MPU can access the DSP
peripheral bus.
MPU Interface
DSP Subsystem
55

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