Texas Instruments OMAP5912 Reference Manual page 947

Table 33. Incoming Interrupt High Register (EDGE_EN_HI)
Bit Name
15:8 Reserved
7 HOST_INTERRUPT
6 NMI
5:0 CHx
Table 34. Incoming Interrupt Low Register (EDGE_EN_LO)
Bit Name
15:0 CHx
4.1.11 DSP Interrupt Handler
SPRU757B
Offset: 0x00
Function
Defines whether the host interrupt from DSP to MPU is
edge-triggered or level-sensitive:
0: HOST_INTERRUPT is level-sensitive.
1: HOST_INTERRUPT is edge-sensitive.
Defines whether the nonmaskable interrupt is edge or
level sensitive:
0: NMI is level-sensitive.
1: NMI is edge-sensitive.
Defines channel CHx as edge-triggered or
level-sensitive, where CHx corresponds to interrupt
channels:
0: CHx is level-sensitive.
1: CHx is edge-sensitive.
Offset: 0x02
Function
This bit defines channel CHx as edge-triggered or
level-sensitive, where CHx corresponds to interrupt
channels:
0: CHx is level-sensitive.
1: CHx is edge-sensitive.
Table 22 lists the DSP registers available to handle interrupts. Table 36
through Table 42 describe the register bits. All these registers are 16 bits wide
and are controlled directly by the DSP private TIPB.
Registers
R/W Reset
R/W 0
R/W 0
R/W 000000
R/W Reset
R/W 0x0000
Interrupts 49