Texas Instruments OMAP5912 Reference Manual page 948

Registers
Table 35. DSP Interrupt Registers
Name
DSP_ITR
DSP_MIR
DSP_SIR_IRQ
DSP_SIR_FIQ
DSP_CONTROL_REG
DSP_SISR
DSP_ILRx
Table 36. Interrupt Register (DSP_ITR)
Bit Name
15:0 ACT_IRQ
Table 37. Mask Interrupt Register (DSP_MIR)
Bit Name
15:0 IRQ_MSK
Table 38. Interrupt Encoded Source Register for IRQ (DSP_SIR_IRQ)
Bit Name
15:4 Reserved
3:0 IRQ_NUM
50 Interrupts
Description
DSP interrupt
DSP mask interrupt
Interrupt encoded source for IRQ
Interrupt encoded source for FIQ
DSP interrupt control
DSP software interrupt set
DSP interrupt level for interrupt number x
Offset: 0x00
Function
If edge-sensitive interrupt occurs, it stores the active
line. The DSP can individually clear each bit by writing
a 0 to the corresponding bit. Writing a 1 keeps its
previous value.
Offset: 0x02
Function
Writing a 1 masks the corresponding interrupt. Each bit
corresponds to one interrupt.
Offset: 0x04
Function
Indicates the encoded interrupt number that has an
IRQ request. Reading this register clears the
corresponding bit in the DSP_ITR if the interrupt is set
as edge-sensitive.
R/W Offset
R/W 0x00
R/W 0x02
R 0x04
R 0x06
R/W 0x08
R/W 0x0A
R/W 0x0C + 0x2 * x
R/W Reset
R/W 0x0000
R/W Reset
R/W 0xFFFF
R/W Reset
R 0000
SPRU757B