Texas Instruments OMAP5912 Reference Manual page 249

Table 106. MPU to DSP Mailbox 1B Register (MPU2DSP1B)
Bit Name
15:0 MPU2DSP1B This register stores the data to be shared
Table 107. DSP to MPU Mailbox 1A Register (DSP2MPU1A)
Bit Name
15:0 DSP2MPU1A This register stores the data to be shared for
Table 108. DSP to MPU Mailbox 1B Register (DSP2MPU1B)
Bit Name
15:0 DSP2MPU1B This register stores the data to be shared for
Table 109. DSP to MPU Mailbox 2A Register (DSP2MPU2A)
Bit Name
15:0 DSP2MPU2A This register stores the data to be shared for
SPRU749A
Base Address = 0xFFFC F000, Offset = 0x04
Function
for the MPU-to-DSP interrupt in mailbox 1.
The MPU2DSP1 interrupt is generated to
DSP when this register is written. When
this register is read by DSP,
(MPU2DSP1_FLAG) is reset.
Base Address = 0xFFFC F000, Offset = 0x08
Function
the DSP-to-MPU interrupt in mailbox 1.
Base Address = 0xFFFC F000, Offset = 0x0C
Function
the DSP-to-MPU interrupt in mailbox 1. The
DSP2MPU1 interrupt is generated to
MPU/DMA/OCP-I when this register is
written. When this register is read by MPU,
(DSP2MPU1_FLAG) is reset.
Base Address = 0xFFFC F000, Offset = 0x10
Function
the DSP-to-MPU interrupt in mailbox 2.
R/W
R/W by MPU/DMA/OCP-I
R by DSP
R/W
R/W by DSP
R by MPU/DMA/OCP-I
R/W
R/W by DSP
R by MPU/DMA/OCP-I
R/W
R/W by DSP
R by MPU/DMA/OCP-I
OMAP3.2 Subsystem
Mailboxes
Reset
0x0000
Reset
0x0000
Reset
0x0000
Reset
0x0000
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