Texas Instruments OMAP5912 Reference Manual page 440

Table 5. Reset Sources for Peripherals (Continued)
Peripheral Name
DSP Interrupt handler 2.1
McBSP1
McBSP3
MCSI1
MCSI2
†
OCP SWRST: Reset software done in corresponding module.
‡
SWRST1: PER_EN (bit 0) in ARM_RSTC2 is cleared to 0.
§
SWRST2: Set ARM_RST (bit 0) in ARM_RSTCT1 and clear DSP_EN (bit 1) in ARM_RSTCT1.
¶
SWRST3: DSP_PEREN (bit 0) in DSP_RSTCT2 is cleared to 0.
#
Warm reset: Source can be MPU_RST, global software reset, or 32-kHz watchdog time-out.
||
SW control via RESET_CONTROL register (see Table 51).
k
SW control via MOD_CONF_CTRL_1[23].
Note: DSP_WD is controlled by the DSP_RSTCT2.WD_PER_EN.
SPRU752B
HW Reset
Class 3 Modules
Cold reset/Warm
reset/ARM_WD/SWRS
T3/SWRST2
Cold reset/Warm
reset/ARM_WD/SWRS
T3/SWRST2
Cold reset/Warm
reset/ARM_WD/SWRS
T3/SWRST2
Cold reset/Warm
reset/ARM_WD/SWRS
T3/ SWRST2/ 32-kHz
WD/ SEC WD /SEC
FSM
Cold reset/Warm
reset/ARM_WD/SWRS
T3/SWRST2/ 32-kHz
WD/SEC WD/ SEC
FSM
SW Reset Wrapper/
Switch
OCP SWRST OCP wrapper
Partial OCP wrapper
Partial OCP wrapper
Partial TIPB
Partial TIPB
Reset Architecture
Wrapper/Switch Reset
Cold reset/Warm
reset/ARM_WD/
DSP_WD/SWRST3/S
WRST2
Cold reset/Warm
reset/ARM_WD/DSP_
WD/SWRST3/SWRST
2
Cold reset/Warm
reset/ARM_WD/DSP_
WD/SWRST3/SWRST
2
Initialization 23