Texas Instruments OMAP5912 Reference Manual page 1089

SPI Master/Slave
Table 9. Set Up SPI 2 Register Bit Description (SPI_SET2—0x028)
Bit Name
31:16 Reserved
15 MODE
14:10 CP
9:5 CE
4:0 CI
Notes: 1) In slave mode, the end of a transaction is detected based on CE field configuration. If CEi = 0, the end of a transaction
is detected on the rising edge of nSPEN0. If CEi = 1, the end of a transaction is detected on the falling edge of
nSPEN0. For more information on the different configurations, see Section 14.1.4.4.
2) In slave mode, all CIi bits must have the same value. This value depends on the inactive edge of the master clock.
3) In slave mode, all CEi bits must have the same value. This value depends on the active level of the master enable.
4) In slave mode, all CPi bits must have the same value. This value depends on the master clock phase.
5) A write access to this register during a transaction does not affect the register and activates an OCP error. The delay
between a write in the SET2 register and the CI/CE bits taking effect is 2 x ARMXOR_CK cycles.
24 Serial Interfaces
Base Address = 0xFFFB 0C00, Offset = 0x28
Function
A read access returns 0.
0: Slave mode
1: Master mode
Clock phase
The shift register clock begins toggling at:
0: The middle of the data transfer
1: The beginning of the data transfer
Bit 10 qualifies the access on device 0.
Bit 11 qualifies the access on device 1.
Bit 12 qualifies the access on device 2.
Bit 13 qualifies the access on device 3.
Bit 14 qualifies the access on device 4.
Shift register enable
Active level of the shift register enable
0: The active level is low.
1: The active level is high.
Bit 5 qualifies the access on device 0.
Bit 6 qualifies the access on device 1.
Bit 7 qualifies the access on device 2.
Bit 8 qualifies the access on device 3.
Bit 9 qualifies the access on device 4.
Clock invert
Inactive edge of the shift register clock
0: The inactive state of the clock is low.
1: The inactive edge of the clock is high.
Bit 0 qualifies the access on device 0.
Bit 1 qualifies the access on device 1.
Bit 2 qualifies the access on device 2.
Bit 3 qualifies the access on device 3.
Bit 4 qualifies the access on device 4.
Access Reset
R 0x0000
R/W 0
R/W 00000
R/W 00000
R/W 00000
SPRU760B