Texas Instruments OMAP5912 Reference Manual page 1012

1 32-Bit Watchdog Timer General Overview
Figure 1. 32-Bit Watchdog
Timer clock
Timer reset
Start/stop
reg(WSPR)
OCP interface to MPU (32-bit)
SPRU759B
This document describes various timers of the OMAP5912 multimedia
processor.
The 32-bit watchdog timer (see Figure 1) is an upward counter that generates
a reset to the ultra-low power device (ULPD) module upon an overflow
condition. This counter can be accessed, loaded, and cleared by accessing
registers through a 16-/32-bit open-core protocol (OCP) interface.
Prescaler
(1:128 ratio)
Control reg
(WCLR)
Shadow reg
(WCRR)
The 32-bit watchdog is an upward 32-bit counter coupled with a prescaler
stage. The prescaler ratio can be set between 1 and 128 clock ratios by
accessing the PTV field and the PRE field of the watchdog control register
(WCLR). Timer value can be accessed on-the-fly by reading the watchdog
counter register (WCRR), modified by accessing the watchdog load register
(WLDR) (no on-the-fly update), or reloaded by following a specific reload
sequence on the watchdog trigger register (WTGR). A specific start/stop
sequence applied to the watchdog start/stop register (WSPR) can start/stop
the watchdog.
Timer (WCRR)
(32-bit counter)
Load reg Write posted
(WLDR) reg (WWPS)
Trig reg
(WTGR)
Timers
Reset to
ULPD
HW revision
reg (WIDR)
Timers 9