Texas Instruments OMAP5912 Reference Manual page 716

System DMA
Table 51. DMA Logical Channel Configuration Registers
Name
DMA_CSDP
DMA_CCR
DMA_CICR
DMA_CSR
DMA_CSSA_L
DMA_CSSA_U
DMA_CDSA_L
DMA_CDSA_U
DMA_CEN
DMA_CFN
DMA_CSFI
DMA_CSEI
DMA_CSAC
DMA_CDAC
DMA_CDEI
DMA_CDFI
DMA_COLOR_L
DMA_COLOR_U
DMA_CCR2
DMA_CLNK_CTRL
DMA_LCH_CTRL
†
n is the logical channel numbered 0x0 through 0xF.
92 Direct Memory Access (DMA) Support
Table 51 lists the logical channel configuration registers. Table 52 through
Table 96 describe the register bits.
Base Address = FFFE D800
Description
Channel source destination parameters
Channel control register
Channel interrupt control register
Channel status register
Channel source start addr, lower bits
Channel source start addr, upper bits
Channel destination start addr, lower bits
Channel destination start addr, upper bits
Channel element number
Channel frame number
Channel source frame index
Channel source element index
Channel source addr counter
Channel destination addr counter
Channel destination element index
Channel destination frame index
Color parameter register, lower bits
Color parameter register, upper bits
Channel control register 2
Channel link control register
Logical channel control register
R/W Offset †
R/W 0x00 + (n*0x40)
R/W 0x02 + (n*0x40)
R/W 0x04 + (n*0x40)
R 0x06 + (n*0x40)
R/W 0x08 + (n*0x40)
R/W 0x0A + (n*0x40)
R/W 0x0C + (n*0x40)
R/W 0x0E + (n*0x40)
R/W 0x10 + (n*0x40)
R/W 0x12 + (n*0x40)
R/W 0x14 + (n*0x40)
R/W 0x16 + (n*0x40)
R 0x18 + (n*0x40)
R 0x1A + (n*0x40)
R/W 0x1C + (n*0x40)
R/W 0x1E + (n*0x40)
R/W 0x20 + (n*0x40)
R/W 0x22 + (n*0x40)
R/W 0x24 + (n*0x40)
R/W 0x28 + (n*0x40)
R/W 0x2A + (n*0x40)
SPRU755B