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Table 47. CLE and ALE
SPRU756A
the FLASH.RDY that is multiplexed with a GPIO. The GPIO is
programmed to create an interrupt on the rising edge of R/B.
Note: FLASH.RDY Signal
The FLASH.RDY signal is primarily intended for use with synchronous burst
flash devices. If the system does have a synchronous burst flash device and
the FLASH.RDY signal is required, then the NAND flash R/B must be con-
nected on some other GPIO of the OMAP161X device. If another GPIO is
used, the interface voltage range must be considered between the open
drain output of the NAND flash and the OMAP5912. Otherwise, it is possible
to remove this input requirement by the use of timers to create the delay and/
or the use polling of the NAND flash device status register.
-
WE and RE: As explained before, during t
require that CS be low and during this time WE and RE must not toggle.
Thus, it is necessary to gate the OMAP161X chip-select, cs2b, with the
FLASH.WE and FLASH.0E signals to create the FLASH.CS2UWE and
FLASH.CS2UOE, respectively.
If the muxed signals are needed in the system, it is possible to generate
WE and RE by GPIO with some performance impact and a more compli-
cated programming model.
-
CLE and ALE: The command latch enable (CLE) and address latch enable
(ALE) signals are generated by the address pins of OMAP161X
FLASH.A[1] and FLASH.A{2}, respectively, as shown in Table 47.
CLE:
ALE:
FLASH.A[1]
FLASH.A[2]
L
L
H
L
L
H
H
H
-
I/O7:0 or I/015:0 : NAND flash devices have either 8- or 16-bit-wide data
buses. The FLASH.D[15] signals of the OMAP161X connect directly to the
NAND flash I/O signals.
Software NAND Flash Controller
some NAND flash devices
R
System Address
(cs2b)
0x0A00 0000
Data read or write access
0x0A00 0002
Command write access
0x0A00 0004
Address write access
0x0A00 0006
Non-valid access condition
Memory Interfaces
Function
79
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